Dynamic Random Access Memories (DRAMs) may have memory precharge, activate, read, and write operations. In particular, a memory controller that addresses a bank of memory must first precharge the memory bank, then the addressed page within the bank must be activated before the addressed column in that page is accessed (read or written). A “DRAM page open” or a “page hit” indicates the memory being accessed has already been precharged and activated, and data may be read or written from the page without having to precharge or activate the memory during each memory access. When a “page miss” occurs (i.e., data is accessed from a page in memory other than from the page that is open), the open page must be written back to the DRAM chip from the sense amps. Next, the new memory page has to first be precharged and activated before being accessed. Writing the old page to DRAM, and precharging and activating the new DRAM pages takes time and slows down memory accesses resulting in an inefficient use of the memory bus (reduced bandwidth) and a loss in performance of an apparatus (e.g., a computer) employing DRAM.
A processor may interface with system memory, including DRAM, by issuing memory access commands over a system bus to a memory controller. A bus interface circuit of the processor may include a bus scheduler that schedules accesses (reads and writes) from the processor to system memory via a bus access queue. If the bus scheduler could place the memory access requests into the bus access queue in an ordering that reduces page misses and enhances page hits, the access latencies may be reduced. It would be possible to make such a bus scheduler if the processor knew both the memory page management implementation and number of pages per bank, normally controlled by the memory controller. However, this information is generally not available for reading from a memory controller.